The present invention relates to the field of computer systems. More particularly, the present invention relates to the field of memory control for computer systems.
The performance of a typical computer system is dependent on memory bandwidth, the speed at which a processor can access memory. One common type of memory used in computer systems is synchronous dynamic random access memory (SDRAM), which is often configured as sets of individual components packaged in dual inline memory modules (DIMMs) that plug into computer motherboards. The speed of SDRAM has increased dramatically, particularly with the development of double data rate (DDR) SDRAM. As the name implies, DDR SDRAMs effectively double memory bandwidth by exchanging data on rising and falling edges of the same clock signal. Unfortunately, the increase in speed has been accompanied by an increase in power consumption.
In an effort to reduce power consumption, some computer systems that use DDR SDRAM devices place the devices into low power states when the devices are not in use. Typically, a set of SDRAM devices, whether single or double data rate, is placed into a low power state by de-asserting the clock enable (CKE) signal for the set of devices. In one method, to take advantage of these low power states, the CKE signal for a given set of SDRAM devices is de-asserted when the set is not being accessed, and asserted when the set is being accessed.
Placing SDRAM devices in low power states, however, decreases memory bandwidth due to an increase in memory system latency. The increase in latency is caused by a delay of one or more clock cycles required by SDRAM devices after the low power state is exited before a valid memory request may be issued to the device. The delay is required to ensure the SDRAM device has achieved a stable condition after powering up, prior to accepting a memory request.
Thus, every time a set of SDRAM devices is powered down, the system incurs a latency penalty of one or more clock cycles. For systems that frequently power down devices in an effort to reduce power consumption, the cumulative effect of these latency periods can degrade system performance substantially. This negative effect on performance increases if memory requests frequently target devices that have been powered down just recently so that the latency periods account for a higher percentage of the access time.